`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:21:03 04/01/2014 
// Design Name: 
// Module Name:    TOP_VGA 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module TOP_VGA(
    output HS,
    output VS,
    output [2:0] red,
    output [2:0] green,
    output [1:0] blue,
    input  clk,
    input  [15:0] data
    );
	 
	 wire pixel_clk;
	 wire [10:0] Hcounter, Vcounter;
	 wire blank;
	 
	 CLK_div25MHz M1 (pixel_clk, clk);
	 VGA_Controller_640x60 M2 (pixel_clk, HS, VS, Hcounter, Vcounter, blank);
	 Display M3 (red, green, blue, Hcounter, Vcounter, blank, clk, data); 

endmodule
